C. Chang, W. Yin, M. Erez, Assessing The Impact of Timing Errors on HPC Applications, In Proceedings of The International Conference for High Performance Computing, Networking, Storage, and Analysis (SC). Denver, CO. November, 2019.
C. Chang, S. Lym, N. Kelly, M. B. Sullivan, M. Erez, Evaluating and Accelerating High-Fidelity Error Injection for HPC, In Proceedings of The International Conference for High Performance Computing, Networking, Storage, and Analysis (SC). Dallas, TX. November, 2018.
Conference Papers
C. Chang, W. Yin, M. Erez, Assessing The Impact of Timing Errors on HPC Applications, In Proceedings of The International Conference for High Performance Computing, Networking, Storage, and Analysis (SC). Denver, CO. November, 2019.
C. Chang, S. Lym, N. Kelly, M. B. Sullivan, M. Erez, Evaluating and Accelerating High-Fidelity Error Injection for HPC, In Proceedings of The International Conference for High Performance Computing, Networking, Storage, and Analysis (SC). Dallas, TX. November, 2018.
O. Subasi, C. Chang, M. Erez, S. Krishnamoorthy, Characterizing the Impact of Soft Errors Affecting Floating-point ALUs using RTL-level Fault Injection, In Proceedings of the 47th International Conference on Parallel Processing (ICPP). Eugene, OR. August, 2018.
S. Lym, H. Ha, Y. Kwon, C. Chang, J. Kim, M. Erez, ERUCA: Efficient DRAM Resource Utilization and Resource Conflict Avoidance for Memory System Parallelism, In Proceedings of High-Performance Computer Architecture (HPCA), Vienna, Austria, February, 2018.
Journal Papers
B. C. Lai, C. Y. Lee, T. H. Chiu, H. K. Kuo, C. K. Chang, Unified Designs for High Performance LDPC Decoding on GPGPU, In IEEE Transactions on Computers, vol.PP, no.99, 2016.
Workshop Papers
C. Chang, G. Li, M. Erez, Evaluating Compiler IR-Level Selective Instruction Duplication with Realistic Hardware Error, Workshop on Fault Tolerance for HPC at eXtreme Scale (FTXS). Denver, CO. November, 2019.
C. Chang, M. Erez, A High-Fidelity, Low-Overhead and Open-Source Timing Error Injector, Workshop on Silicon Errors in Logic–System Effects (SELSE). Palo Alto, CA. March, 2019.
C. Chang, S. Lym, N. Kelly, M. B. Sullivan, M. Erez, Hamartia: A Fast and Accurate Error Injection Framework, Workshop on Silicon Errors in Logic–System Effects (SELSE). Boston, MA. April, 2018. Best of SELSE (invited to present at DSN 2018)
H. Menon, C. Chang, K. Mohror and M. Erez, Identifying Critical Variables Using Algorithmic Differentiation for a Realistic Fault Model, Workshop on Silicon Errors in Logic–System Effects (SELSE). Boston, MA. April, 2018.
